Approximate Computing on FPGAs for Edge Computing Applications: A Case Study of Adaptive Filters

Efficient Coplanar Arithmetic Circuits in QCA Using a Pseudo 2:1 Multiplexer

Coplanar High‐Speed and Efficient Multiplier Design for QCA Technology

Enhanced Radiation Tolerance of a Remote Interface Unit Using Commercial-Off-The-Shelf Components for Space Applications

On the Design of Iterative Approximate Floating-Point Multipliers

Logarithm-approximate floating-point multiplier

On the design of radix-K approximate multiplier using 2D pseudo-booth encoding

Memristor Crossbar-Based Hardware Implementation of Type-2 Fuzzy Membership Function and On-Chip Learning

Investigation and feasibility study of using components with different categories from the perspective of radiation damage in LEO and GEO orbits

Fault Tolerant ALU Designing based on New Implementation of Berger Code

Design of low power approximate floating‐point adders

Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes

A Survey on the Best Choice for Modulus of Residue Code

An Efficient Current Mode MVL Residue Code Checker for Fault Tolerant Arithmetic

Novel Metamaterial Compact Planar MIMO Antenna Systems with Improved Isolation for WLAN Application

An FPGA-based Design Approach for Microsatellites Telemetry Subsystem

New Protection Technique Against Unidirectional MEUs for FIR Filters

Implementation of AHP-based reliability allocation for control and monitoring subsystem

Reliability and Performance Analysis of a Fault Tolerant Data Handling Protocol for Aerospace Applications

Designing and implementing a reliable thermal monitoring system based on the 1-wire protocol on FPGA for a LEO satellite

Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators

SEU-SECURE PARITY PREDICTION MULTIPLIER ON SRAM-BASED FPGAs

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

HYBRID REDUNDANCY APPROACH TO INCREASE THE RELIABILITY OF FPGA BASED SPEED CONTROLLER CORE FOR HIGH SPEED TRAIN1

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS1

Dynamic Partial based Single Event Upset (SEU) Injection Platform on FPGA

SEU Rate and Reliability Analysis in LEO Satellites

New Circuit Level Radiation Tolerant Method to Mitigate Total Ionizing Dose on FPGA

Ultra-Low-Latency QCA Adder Design Using an Innovative Carry Generato

Error Analysis and Evaluation of Approximate Adder Circuits in 180nm Technology

Design and simulation of DC machine signal based on PID control and Matlab Simulink to eliminate distortion

Categorizing of Persian news topics using eye-tracking models

Evaluation of the effect of gamma radiation on the Wilkinson power divider of the CRLH-A coupled line for use in geo-satellites

مشخصات نویسندگان مقاله طراحی و شبیه سازی LNA با فرکانس 2.45GHZ در تکنولوژی CMOS 0.18um

مروری بر روش های ارزیابی تاثیر خطای های محیط هوافضا بر میکروالکترونیک و ارائه بستر تست خطای SEE

Speed Controller System Based on FPGA for High Speed Train

طراحی و پیاده سازی لینک های مطمئن جهت تبادل داده با نرخ پایین در یک ماهوارهLEO

تعیین مجموعه دستورات تله کامند ماهواره با قابلیت اطمینان بالا

افزایش مصونسازی نسبت به SEU با رویکرد پخش کامل مدار انتخابگر در FPGA